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F25L08QA-50PG2S 参数 Datasheet PDF下载

F25L08QA-50PG2S图片预览
型号: F25L08QA-50PG2S
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 8MX1, PDSO8, 0.150 INCH, 1.27 MM PITCH, ROHS COMPLIANT, SOIC-8]
分类和应用: 时钟光电二极管内存集成电路
文件页数/大小: 43 页 / 355 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L08QA (2S)  
Deep Power Down (DP)  
The Deep Power Down instruction is for minimizing power  
consumption (the standby current is reduced from ISB1 to ISB2.).  
Once the device is in deep power down status, all instructions will  
be ignored except the Release from Deep Power Down  
instruction (RDP) and Read Electronic Signature instruction  
(RES). The device always power-up in the normal operation with  
the standby current (ISB1). See Figure 24 for the Deep Power  
Down instruction.  
This instruction is initiated by executing an 8-bit command, B9H,  
and then CE must be driven high. After CE is driven high, the  
device will enter to deep power down within the duration of TDP  
.
CE  
MODE3  
0
1
2
3
4
5
6
7
TDP  
SCK MODE0  
B9  
SI  
MSB  
Standard Current  
Deep Power Down Current  
(ISB2)  
Figure 24: Deep Power Down Instruction  
Release from Deep Power Down (RDP) and Read Electronic-Signature (RES)  
The Release form Deep Power Down and Read  
Electronic-Signature instruction is a multi-purpose instruction.  
CE low and executing an 8-bit command, ABH, followed by 3  
dummy bytes. The Electronic-Signature byte is then output from  
the device. The Electronic-Signature can be read continuously  
The instruction can be used to release the device from the deep  
power down status. This instruction is initiated by driving CE  
until CE go high. See Figure 26 for RES sequence. After  
driving CE high, it must remain high during for the duration of  
TRES2, and then the device will resume normal operation and  
other instructions are accepted.  
low and executing an 8-bit command, ABH, and then drive CE  
high. See Figure 25 for RDP instruction. Release from the deep  
power down will take the duration of TRES1 before the device will  
resume normal operation and other instructions are accepted.  
The instruction is executed while an Erase, Program or WRSR  
cycle is in progress is ignored and has no effect on the cycle in  
progress. In OTP mode, user also can execute RES to confirm  
the status of OTP.  
CE must remain high during TRES1  
.
The instruction also can be used to read the 8-bit Electronic-  
Signature of the device on the SO pin. It is initiated by driving  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Nov. 2013  
Revision: 1.2  
28/43  
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