ESMT
F25L08QA (2S)
Write Status Register (WRSR)
The Write Status Register instruction writes new values to the
BP3, BP2, BP1, BP0, QE and BPL (Status Register-1) bits of the
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1, BP2 and BP3 bits in the status
status register. CE must be driven low before the command
sequence of the WRSR instruction is entered and driven high
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
before the WRSR instruction is executed. CE must be driven
high after the eighth bit of data that is clocked in. If it is not done,
the WRSR instruction will not be issued. See Figure 21 for
WREN and WRSR instruction sequences.
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1, BP2 and BP3
bits at the same time. See Table 4 for a summary description of
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
WP and BPL functions.
CE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MODE3
MODE0
SCK
Stauts Register-1
Data In
06
01
7
6
4
3
2
0
1
SI
5
MSB
MSB
HIGH IMPENANCE
SO
Figure 21: Write Enable (WREN) and Write Status Register (WRSR)
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation. When a Write
operation is in progress, the BUSY bit may be checked before
sending any new commands to assure that the new commands
are properly received by the device.
and remain low until the status data is read. The RDSR-1
instruction code is “05H” for Status Register-1. The RDSR-2
instruction code is “35H” for Status Register-2. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 22
for the RDSR instruction sequence.
CE must be driven low before the RDSR instruction is entered
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK MODE0
05 or 35
SI
MSB
HIGH IMPEDANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status Register -1 or -2 Data Out
Figure 22: Read Status Register (RDSR-1 or RDSR-2) Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 26/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
