ESMT
F25L08QA (2S)
Erase Suspend
The Erase Suspend instruction allows the system to interrupt a
Sector or Block Erase operation and then read from any other
sector or block. The Write Status Register instruction and Sector /
Block Erase instructions are not allowed during suspend. Erase
Suspend is valid only during the Sector or Block Erase operation.
If written during the Chip Erase or Program operation, the Erase
Suspend instruction is ignored. A maximum of TSUS is required to
suspend the erase operation. The BUSY bit in the Software
Status Register will clear to “0” after Erase Suspend. A power-off
during the suspend period will reset the device and release the
suspend status.
CE
0
1
2
3
4
5
6
7
MODE3
TSUS
SCK MODE0
SI
75
MSB
HIGH IMPEDANCE
SO
Accept Read or Program Instruction
Figure 17: Erase Suspend Instruction
Erase Resume
The Erase Resume instruction must be written to resume the
Sector or Block Erase operation after Erase Suspend. After
issued the BUSY bit in the Software Status Register will be set to
“1” and the sector or block will complete the erase operation.
Erase Resume instruction will be ignored unless an Erase
Suspend operation is active.
CE
0
1
2
3
4
5
6
7
MODE3
SCK MODE0
SI
7A
MSB
Resume Sector or Block Erase
Figure 18: Erase Resume Instruction
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
24/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
