ESMT
F25L08QA (2S)
Fast Read Dual Output (50 MHz ~ 100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on bidirectional I/O pins (SIO0 and SIO1). This allows data to be
transferred from the device at twice the rate of standard SPI
devices. This instruction is for quickly downloading code from
Flash to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
CE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
43 44
MODE3
MODE0
47 48
51 52
55 56
SCK
SIO0
IO0 switches from Input to Ouput
Dummy
3B
ADD.
MSB
ADD.
ADD.
6
7
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
1
6
7
4
MSB
DOUT
N
DOUT
N+1
DOU T
N+2
DOU T
N+3
DOUT
N+4
5
HIGH IMPENANCE
SIO1
5
1
7
5
1
7
5
1
7
5
3
3
3
3
Note: The input data during the dummy clocks is “don’t care”.
However , the IO0 pin should be high-impefance piror to the falling edge of the first data clock.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 15/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
