ESMT
F25L08QA (2S)
Fast Read Quad I/O (50 MHz ~ 100 MHz)
The Fast Read Quad I/O (EBH) instruction is similar to the Fast
Read Quad Output (6BH) instruction, but with the capability to
input address bits [A23 -A0] four bits per clock. A Quad Enable
(QE) bit of Status Register-1 must be set “1” to enable Quad
function.
If [M7 –M0] = “AxH”, the next Fast Read Quad I/O instruction (after
CE is raised and the lowered) doesn’t need the command code
(See Figure 9). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M7 –M0] are the value other than “AxH”, the next
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M7 –M0] before issuing normal instructions.
To set mode bits [M7 -M0] after the address bits [A23 -A0] can
further reduce instruction overhead (See Figure 8). The upper
mode bits [M7 –M4] controls the length of next Fast Read Quad
I/O instruction with/without the first byte command code (EBH).
The lower mode bits [M3 –M0] are “don’t care”.
CE
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MODE3
MODE0
SCK
IO0 switches from Input to Ouput
Dummy
20
16 12
8
4
5
0
1
4
EB
0
1
4
0
0
4
0
SIO0
SIO1
4
MSB
HIGH IMPENANCE
HIGH IMP ENANCE
HIGH IMP ENANCE
21 17 13
22 18 14
5
9
5
1
5
1
5
1
SIO2
6
7
2
3
10
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
SIO3
23 19 15 11
A23- 0
M7-0
N
N+1 N+2
DOUT DOUT DOUT
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 8: Fast Read Quad I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE
0
1
2
3
8
4
5
6
7
8
9 10 11 12 13 14 15 16
MODE3
MODE0
SCK
IO0 switches from Input to Ouput
Dummy
20
16 12
4
5
0
1
4
5
0
1
4
5
0
1
0
4
5
0
1
4
5
SIO0
SIO1
21 1 7 13
22 18 14
9
1
6
7
2
3
10
6
7
2
3
6
7
2
3
6
7
2
3
SIO
2
6
7
2
3
23 19 15 11
SIO
3
A23-0
M7-0
N
N+1 N+2
DOUT DOUT DOU T
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 9: Fast Read Quad I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 18/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
