ESMT
F25L08QA (2S)
16. M7-M0: Mode bits. Quad input address:
IO
IO
IO
IO
0
1
2
3
= (A20, A16, A12, A
= (A21, A17, A13, A
= (A22, A18, A14, A10, A
8
, A
4
, A
, A
0
, M
4
, M
, M
0
)
)
2
9
, A5
1
, M5
1
6
, A
2
, M
6
, M
)
)
= (A23, A19, A15, A11, A
7
, A
3
, M
7
, M
3
Bus Cycle-2
Fast Read Quad I/O data:
IO
IO
IO
IO
0
1
2
3
= (X, X), (X, X), (D
= (X, X), (X, X), (D
= (X, X), (X, X), (D
= (X, X), (X, X), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
) (D
) (D
) (D
) (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
)
)
)
)
), (D
), (D
), (D
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
Bus Cycle-3
Bus Cycle-4
17. The instruction is initiated by executing command code, followed by address bits into SI (SIO0) before DIN, and then input
data to bidirectional IO pins (SIO0 ~ SIO3).
Quad input data:
IO
IO
IO
IO
0
1
2
3
= (D
= (D
= (D
= (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
)
)
)
)
DIN0
DIN1
DIN2
DIN3
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 13/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
