ESMT
F25L08QA (2S)
Fast Read Dual I/O (50 MHz ~ 100 MHz)
The Fast Read Dual I/O (BBH) instruction is similar to the Fast
Read Dual Output (3BH) instruction, but with the capability to
input address bits [A23 -A0] two bits per clock.
If [M7 –M0] = “AxH”, the next Fast Read Dual I/O instruction (after
CE is raised and the lowered) doesn’t need the command code
(See Figure 6). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M7 –M0] are the value other than “AxH”, the next
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M7 –M0] before issuing normal instructions.
To set mode bits [M7 -M0] after the address bits [A23 -A0] can
further reduce instruction overhead (See Figure 5). The upper
mode bits [M7 –M4] controls the length of next Fast Read Dual I/O
instruction with/without the first byte command code (BBH). The
lower mode bits [M3 –M0] are “don’t care”.
CE
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
27 28
31 32
35 36
39 40
MODE3
MODE0
SCK
SIO0
IO0 switches from Input to Ouput
22
2
20 18 16 14 12 10
6
4
5
0
1
6
4
BB
8
9
6
7
4
2
0
6
4
2
0
6
4
2
0
6
4
2 0
6
7
4
MSB
DOUT
N
DOU T
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
5
HIGH IMPENANCE
SIO1
23 21 19
11
7
3
7
5
M7-0
17 15 13
5
1
7
5
1
7
5
1
7
5
1
3
3
3
3
A23-16 A15-8
A7- 0
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 5: Fast Read Dual I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE
SCK
SIO0
MODE3
MODE0
0 1 2 3 4 5 6 7 8 9 10 11 121314 15 16
1920
2324
2728
3132
IO0 switches from Input to Ouput
22
2
20 18 16 14 12 10
6
4
0
1
6
4
8
6
7
4
2
0
1
6
7
4
2
0
1
6
7
4
2
0
1
6
7
4
2
0
1
6
7
4
DOUT
N
DOUT
N+1
DOU T
N+2
DOUT
N+3
DOUT
N+4
5
SIO1
23 21 19
11
9
7
5
3
7
5
17 15 13
5
5
5
5
3
3
3
3
A23-16 A15- 8
A7-0
M7-0
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 6: Fast Read Dual I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 16/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
