ESMT
Table 3: Block Protection Table
Protection Level
0
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Upper 7/8
Upper 15/16
Bottom 1/16
Bottom 1/8
Bottom 1/4
Bottom 1/2
Bottom 7/8
Bottom 15/16
All Blocks
Status Register Bit
BP3
X
0
0
0
0
0
0
1
1
1
1
1
1
X
BP2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F25L08QA (2S)
Protected Memory Area
64KB Block Range
None
Block 15
Block 14~15
Block 12~15
Block 8~15
Block 2~15
Block 1~15
Block 0
Block 0~1
Block 0~3
Block 0~7
Block 0~13
Block 0~14
Block 0~15
Address Range
None
0F0000H – 0FFFFFH
0E0000H – 0FFFFFH
0C0000H – 0FFFFFH
080000H – 0FFFFFH
020000H – 0FFFFFH
010000H – 0FFFFFH
000000H – 00FFFFH
000000H – 01FFFFH
000000H – 03FFFFH
000000H – 07FFFFH
000000H – 0DFFFFH
000000H – 0EFFFFH
000000H – 0FFFFFH
Block Protection (BP3, BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP3, BP2, BP1 and BP0 bits as long as
WP
is high or the
Block- Protection-Look (BPL) bit is 0. Chip Erase can only be
executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory
default setting for Block Protection Bit (BP3 ~ BP0) is 0.
Block Protection Lock-Down (BPL)
WP
pin driven low (V
IL
), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When
the
WP
pin is driven high (V
IH
), the BPL bit has no effect and its
value is “Don’t Care”.
Quad Enable (QE)
When the Quad Enable bit is reset to “0” (factory default),
WP
and HOLD pins are enabled. When QE pin is set to “1”, Quad
SIO
2
and SIO
3
are enabled. (The QE should never be set to “1”
during standard and Dual SPI operation if the
WP
and HOLD
pins are tied directly to the V
DD
or V
SS
.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
9/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
