EN29LV160A
Table 10. Status Register Bits
DQ
Name
Logic Level
Definition
Erase Complete or
erase Sector in Erase
suspend
‘1’
‘0’
Erase On-Going
DATA#
POLLING
7
Program Complete or
data of non-erase Sector
during Erase Suspend
DQ7
DQ7#
‘-1-0-1-0-1-0-1-’
DQ6
Program On-Going
Erase or Program On-going
Read during Erase Suspend
TOGGLE
BIT
6
Erase Complete
‘-1-1-1-1-1-1-1-‘
‘1’
‘0’
‘1’
‘0’
Program or Erase Error
Program or Erase On-going
Erase operation start
5
3
ERROR BIT
ERASE
TIME BIT
Erase timeout period on-going
Chip Erase, Erase or Erase
suspend on currently
addressed
Sector. (When DQ5=1, Erase
Error due to currently
TOGGLE
BIT
2
‘-1-0-1-0-1-0-1-’
DQ2
addressed Sector. Program
during Erase Suspend on-
going at current address
Erase Suspend read on
non Erase Suspend Sector
Notes:
DQ7 DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5
for Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Error Bit: set to “1” if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
20
Rev. I, Issue Date: 2008/07/17
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
