Page 84
Epson Research and Development
Vancouver Design Center
7.5.2 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPDAT[7:0]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
FPDAT7
FPDAT6
1-1
1-2
1-3
1-4
1-5
1-9
1-10
1-11
1-12
1-13
FPDAT5
FPDAT4
FPDAT3
FPDAT2
1-6
1-7
1-14
1-15
FPDAT1
FPDAT0
1-8
1-16
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-24: Single Monochrome 8-Bit Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
