Epson Research and Development
Page 15
Vancouver Design Center
MCLK
These settings select the signal source and input clock
divisor for the memory clock (MCLK). MCLK should
be set based on the type and speed of DRAM as follows.
Optimal Memory Clock (MCLK)
Memory Type
50ns
40MHz
—
60ns
70ns
EDO
FPM
33MHz
25MHz
30MHz
20MHz
Source
Selects the MCLK source. Possible sources include
CLKI or BUSCLK. Typically MCLK is derived from
BUSCLK.
Divide
Timing
Specifies the divide ratio for the clock source signal.
Unless the MCLK source frequency is very high,
resulting in more than a 50MHz MCLK, this ratio
should be set at 1:1.
This field shows the actual MCLK frequency used by
the configuration process.
MediaPlugCLK
These settings select the signal source and input clock
divide for the MediaPlug clock (MediaPlugCLK).
Source
Divide
Timing
Selects the MediaPlug clock source.
Selects the divide ratio for the MediaPlug clock source.
This field shows the actual MediaPlugCLK frequency
used by the configuration process.
13506CFG Configuration Program
Issue Date: 01/03/14
S1D13506
X25B-B-001-02
EPSON [ EPSON COMPANY ]
