Page 14
Epson Research and Development
Vancouver Design Center
LCD PCLK
These settings select the signal source and input clock
divisor for the panel pixel clock (LCD PCLK).
Source
Selects the LCD PCLK source. Possible sources include
CLKI, CLKI2, BUSCLK or MCLK. Typically the LCD
PCLK is derived from CLKI.
Divide
Specifies the divide ratio for the clock source signal.
Selecting “Auto” for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is being specified, it is
best to leave this setting on “Auto”.
Timing
CRT/TV PCLK
Source
This field shows the actual LCD PCLK used by the
configuration process.
These settings select the signal source and input clock
divisor for the CRT/TV pixel clock (CRT/TV PCLK).
Selects the CRT/TV PCLK source. Possible sources
include CLKI, CLKI2, BUSCLK or MCLK. Typically
the CRT/TV PCLK is derived from CLKI.
Divide
Timing
Specifies the divide ratio for the clock source signal.
Selecting “Auto” for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is required, it is best to
leave this setting on “Auto”.
This field shows the actual CRT/TV PCLK used by the
configuration process.
S1D13506
X25B-B-001-02
13506CFG Configuration Program
Issue Date: 01/03/14
EPSON [ EPSON COMPANY ]
