Epson Research and Development
Page 25
Vancouver Design Center
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Oscillator
Oscillator
PC Card
BUS
VDD
A0
FPDAT[15:8]
FPDAT[7:0]
FPSHIFT
UD[7:0]
LD[7:0]
16-bit
Dual
LCD
Decoder
M/R#
A[25:21]
FPSHIFT
Decoder
CS#
FPFRAME
FPLINE
DRDY
FPFRAME
FPLINE
Display
A[20:1]
D[15:0]
AB[20:1]
DB[15:0]
DRDY (MOD)
WE#
WE0#
WE1#
S1D13506
CE2#
GPIOx
OE#
RD#
CE1#
RED,GREEN,BLUE
HRTC
RD/WR#
WAIT#
WAIT#
CRT/TV
Display
VRTC
RESET
RESET#
BUSCLK
IREF
Oscillator
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-8: Typical System Diagram (PC Card Bus)
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Oscillator
Oscillator
PR31500
/PR31700
BUS
M/R#
CS#
FPDAT[7:4]
FPDAT[3:0]
FPSHIFT
UD[3:0]
8-bit
Dual
LD[3:0]
BS#
AB[16:13]
AB[12:0]
FPSHIFT
A[12:0]
D[23:16]
LCD
DB[15:8]
DB[7:0]
AB20
D[31:24]
ALE
FPFRAME
FPLINE
FPFRAME
FPLINE
DRDY
Display
/CARDREG
AB19
AB18
AB17
DRDY (MOD)
/CARDIORD
/CARDIOWR
/CARDxCSH
S1D13506
GPIOx
WE1#
RD/WR#
RD#
/CARDxCSL
/RD
RED,GREEN,BLUE
HRTC
CRT/TV
Display
/WE
WE0#
WAIT#
VRTC
/CARDxWAIT
DCLKOUT
RESET#
BUSCLK
RESET#
IREF
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-9: Typical System Diagram (Philips MIPS PR31500/PR31700 Bus)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
