Page 24
Epson Research and Development
Vancouver Design Center
Oscillator
Oscillator
PowerPC
BUS
A[0:10]
M/R#
CS#
Decoder
Decoder
16-bit
Single
FPDAT[15:0]
FPSHIFT
D[15:0]
FPSHIFT
LCD
A[11:31]
D[0:15]
AB[20:0]
DB[15:0]
FPFRAME
FPLINE
DRDY
FPFRAME
Display
FPLINE
DRDY (MOD)
BI#
WE1#
BS#
TS#
S1D13506
RD/WR#
TSIZ0
TSIZ1
TA#
GPIOx
RD/WR#
RD#
RED,GREEN,BLUE
HRTC
WE0#
WAIT#
CRT/TV
Display
VRTC
CLKOUT
RESET#
BUSCLK
RESET#
IREF
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-6: Typical System Diagram (Motorola PowerPC Bus)
.
Oscillator
Oscillator
MIPS
BUS
M/R#
CS#
A[25:21]
CSn#
Decoder
8-bit
FPDAT[7:0]
FPSHIFT
D[7:0]
Single
LCD
FPSHIFT
A[20:0]
D[15:0]
AB[20:0]
DB[15:0]
FPFRAME
FPLINE
DRDY
FPFRAME
FPLINE
Display
DRDY (MOD)
MEMW#
SBHE#
WE0#
WE1#
S1D13506
GPIOx
MEMR#
RD#
VDD
RED,GREEN,BLUE
HRTC
RD/WR#
BS#
CRT/TV
Display
RDY
BCLK
WAIT#
VRTC
BUSCLK
RESET#
RESET
IREF
IREF
1Mx16
FPM/EDO-DRAM
Figure 3-7: Typical System Diagram (NECVR41xx MIPS Bus)
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
