Epson Research and Development
Page 23
Vancouver Design Center
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Oscillator
Oscillator
MC68000
BUS
VDD
RD#
WE0#
FPDAT[7:4]
FPDAT[3:0]
FPSHIFT
UD[3:0]
8-bit
Dual
LD[3:0]
A[23:21]
FC0, FC1
M/R#
Decoder
FPSHIFT
LCD
CS#
Decoder
FPFRAME
FPLINE
DRDY
FPFRAME
FPLINE
Display
A[20:1]
D[15:0]
AB[20:1]
DB[15:0]
DRDY (MOD)
LDS#
AB0
S1D13506
UDS#
AS#
WE1#
BS#
GPIOx
RED,GREEN,BLUE
HRTC
R/W#
RD/WR#
WAIT#
DTACK#
CRT/TV
Display
VRTC
CLK
BUSCLK
RESET#
RESET#
IREF
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-4: Typical System Diagram (MC68K Bus 1, Motorola 16-Bit 68000)
.
Oscillator
Oscillator
MC68030
BUS
A[31:21]
FC0, FC1
M/R#
CS#
Decoder
Decoder
FPDAT[8:0]
FPSHIFT
D[8:0]
9-bit
TFT
FPSHIFT
A[20:0]
AB[20:0]
DB[15:0]
FPFRAME
FPLINE
DRDY
FPFRAME
FPLINE
D[31:16]
Display
DRDY (MOD)
DS#
AS#
WE1#
BS#
S1D13506
R/W#
SIZ1
GPIOx
RD/WR#
RD#
RED,GREEN,BLUE
HRTC
SIZ0
WE0#
WAIT#
DSACK1#
CRT/TV
Display
VRTC
CLK
BUSCLK
RESET#
RESET#
IREF
IREF
256Kx16
FPM/EDO-DRAM
Figure 3-5: Typical System Diagram (MC68K Bus 2, Motorola 32-Bit 68030)
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
