Epson Research and Development
Page 39
Vancouver Design Center
7.2.1 Registers
REG[040h] LCD Display Mode Register
LCD
Bit-per-pixel
Select Bit 2
LCD
Bit-per-pixel
Select Bit 1
LCD
Bit-per-pixel
Select Bit 0
LCD Display
Blank
SwivelView
Enable Bit 1
n/a
n/a
n/a
When set to 1, this bit disables the LCD display pipeline and forces all LCD data outputs
to zero. This effectively blanks the screen.
Note
If a dual panel is used, the Dual Panel Buffer must be disabled before blanking the LCD
display. This is done by setting REG[041h] bit 0 to 1b.
7.2.2 Enabling the LCD Panel
If the LCD bias power supply timing requirements are different than those timings built into
the S1D13506 automated LCD power sequencing, it may be necessary to manually enable
the LCD panel. In such a case, the following procedure applies.
1. Enable the LCD signals - Set REG[040h] = 0.
Note
If a dual panel is used, enable the Dual Panel Buffer by setting REG[041h] bit 0 = 0b.
2. Enable GPIO1 to activate the LCD bias power.
7.2.3 Disabling the LCD Panel
If the LCD bias power supply timing requirements are different than those timings built into
the S1D13506 automated LCD power sequencing, it may be necessary to manually disable
the LCD panel. In such a case, the following procedure applies.
1. Disable the LCD power using GPIO1.
2. Wait the required delay time for the LCD bias power supply to discharge.
3. Disable the LCD signals - Set REG[040h] = 1.
4. Disable the LCD pixel clock source if desired. (Optional)
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03