Epson Research and Development
Page 37
Vancouver Design Center
6.2.3 DRAM Refresh Selection
REG[021h] DRAM Refresh Rate Register
DRAM
Refresh Rate Refresh Rate Refresh Rate
Bit 2 Bit 1 Bit 0
DRAM
DRAM
Refresh
Select Bit 1
Refresh
Select Bit 0
n/a
n/a
n/a
The Refresh Select bits specify the type of DRAM refresh used while Power Save Mode is
enabled. DRAM refresh selection is as follows.
Table 6-1: Refresh Selection
Refresh Select Bits [1:0]
DRAM Refresh Type
CAS-before-RAS (CBR) refresh
Self-Refresh
00
01
1X
No Refresh
The Refresh Select bits must be set before Power Save Mode is enabled. While CBR refresh
is selected the memory controller cannot be powered down and the memory clock source
must remain active. If either self-refresh or no refresh is selected the memory controller
may be powered down and the memory clock source may be disabled. For further infor-
mation, see Section 6.2.2, “Power Save Status Bits” on page 36.
Note
The Refresh Select bits must not be changed while in power save mode.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
EPSON [ EPSON COMPANY ]
