Page 108
Epson Research and Development
Vancouver Design Center
7.5.10 Dual Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPDAT[15:0]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
1-R1,
1-B3,
1-G638,
241-B3
FPDAT[15,7]
FPDAT[14,6]
FPDAT[13,5]
FPDAT[12,4]
241-R1
241-G638
1-G1,
241-G1
1-R4,
241-R4
1-B638,
241-B638
1-G4,
241-G4
1-R639,
241-R639
1-B1,
241-B1
1-R2,
241-R2
1-B4,
241-B4
1-G639,
241-G639
1-B639,
241-B639
1-G2,
241-G2
1-R5,
241-R5
FPDAT[11,3]
FPDAT[10,2]
FPDAT[9,1]
FPDAT[8,0]
1-G5,
1-R640,
1-B2,
241-G5
241-R640
241-B2
1-R3,
241-R3
1-B5,
241-B5
1-G640,
241-G640
1-G3,
241-G3
1-R6,
241-R6
1-B640,
241-B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-41: Dual Color 16-Bit Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
