Epson Research and Development
Page 105
Vancouver Design Center
7.5.9 Dual Color 8-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPDAT[7:0]
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
FPDAT7
1-G2
1-G6
1-B7
1-B639
1-R1
1-B3
1-R4
1-R5
1-G5
1-B5
1-R6
1-B2
1-R3
1-G3
1-B6
1-R7
1-G7
1-R8
1-G8
1-R640
1-G640
1-B640
1-G1
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
1-B1
1-G4
1-B4
1-B8
1-R2
241-
B639
241-B7
241-G2 241-B3 241-R5 241-G6
241-R1
241-G1 241-B2
241-
R640
241-R4 241-G5
241-R8
241-G8
241-B6
241-
G640
241-B1 241-R3 241-G4 241-B5 241-R7
241-G3 241-B4 241-G7
FPDAT1
FPDAT0
241-
B640
241-R2
241-R6
241-B8
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-39: Dual Color 8-Bit Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
