EM47FM3288SBB
Pin Capacitance
Symbol
Parameters
Pins
Min.
0.8
0
Max. Unit
Notes
1,3
CCK
Input pin capacitance, CK, /CK
CK, /CK
1.4
pF
pF
CDCK
Delta input pin capacitance, CK,
/CK
0.15
1,2
CIN_CTRL
Input pin capacitance, control pins /CS,CKE,ODT
0.75
-0.4
1.3
0.2
pF
pF
1
CDIN_CTRL
Delta input pin capacitance,
control pins
1,4
CIN_ADD_CMD
CDIN_ADD_CMD
Input pin capacitance, address
and command pins
/RAS,/CAS,/WE,
Address
0.75
-0.4
1.3
0.4
pF
pF
1
Delta input pin capacitance,
address and command pins
1,5
CIO
Input/output pins capacitance
DQ,DQSU,/DQSU 1.5
2.5
0.3
pF
pF
1,6
DQSL,/DQSL,
CDIO
Delta input/output pins
capacitance
-0.5
1,7,8
DMU, DML
CDDQS
CZQ
Delta input/output pins
capacitance
DQS, /DQS
ZQ
0
-
0.15
3
pF
pF
1,10
1,9
Input/output pin capacitance, ZQ
Notes1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the pin under test) floating.
VDD = VDDQ =1.5V, VBIAS=VDD/2.
Notes2. Absolute value of CCK(CK-pin) - CCK(/CK-pin).
Notes3. CCK (min.) will be equal to CIN (min.)
Notes4. CDIN_CTRL = CIN_CTRL - 0.5*(CCK(CK-pin) + CCK(/CK-pin))
Notes5. CDIN_ADD_CMD = CIN_ADD_CMD - 0.5*(CCK(CK-pin) + CCK(/CK-pin))
Notes6. Although the DMU and DML pins have different functions, the loading matches DQ and DQS.
Notes7. DQ should be in high impedance state.
Notes8. CDIO = CIO (DQ, DM) - 0.5*(CIO(DQS-pin) + CIO(/DQS-pin)).
Notes9. Maximum external load capacitance on ZQ pin is 5pF.
Notes10. Absolute value of CIO(DQS) - CIO(/DQS).
Jul. 2012
7/41
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