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EM47FM3288SBB 参数 Datasheet PDF下载

EM47FM3288SBB图片预览
型号: EM47FM3288SBB
PDF下载: 下载PDF文件 查看货源
内容描述: 16GB ( 64mA的?? 8Bankà ?? 32 ),双数据速率3 SDRAM堆叠 [16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM]
分类和应用: 动态存储器
文件页数/大小: 41 页 / 1147 K
品牌: EOREX [ EOREX CORPORATION ]
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EM47FM3288SBB  
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended  
components of differential signals have a requirement with respect to VDD/2; this is nominally the same.  
The transition of single-ended signals through the AC-levels is used to measure setup time. For singleended  
components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but  
adds a restriction on the common mode characteristics of these signals.  
Single-ended levels for CK, DQS, /CK, /DQS  
Note  
Symbol  
VSEH  
Parameter  
Min.  
Max.  
Units  
Single-ended high-level for strobes  
Single-ended high-level for CK, /CK  
Single-ended low-level for strobes  
Single-ended low-level for CK, /CK  
(VDD/2)+0.175  
(VDD/2)+0.175  
See Note3  
See Note3  
See Note3  
V
V
V
V
1,2  
1,2  
1,2  
1,2  
(VDD/2)-0.175  
(VDD/2)-0.175  
VSEL  
See Note3  
Note1. For CK, /CK use VIH/VIL(AC) of address/command; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.  
Note2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on  
VREFCA; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level  
applies also here.  
Note3. These values are not defined, however the single-ended components of differential signals CK, /CK,  
DQS, /DQS need to be within the respective limits (VIH(DC) max, VIL(DC) min) for single-ended signals  
as well as the limitations for overshoot and undershoot.  
Jul. 2012  
10/41  
www.eorex.com  
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