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EM47FM3288SBB 参数 Datasheet PDF下载

EM47FM3288SBB图片预览
型号: EM47FM3288SBB
PDF下载: 下载PDF文件 查看货源
内容描述: 16GB ( 64mA的?? 8Bankà ?? 32 ),双数据速率3 SDRAM堆叠 [16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM]
分类和应用: 动态存储器
文件页数/大小: 41 页 / 1147 K
品牌: EOREX [ EOREX CORPORATION ]
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EM47FM3288SBB  
Mode Register Definition  
Mode Register MR0  
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls  
burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge  
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various  
applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0, BA1 and BA2, while  
controlling the states of address pins according to the table below.  
BA2 BA1 BA0 A13 A12 A11 A10  
A9  
A8  
A7  
TM  
A6  
A5  
A4  
A3  
A2  
CL  
A1  
A0  
0
0 0  
0
PPD  
WR  
DLL  
CAS Latency  
RBT  
BL  
DLL Control  
A12  
DLL Reset  
No  
A8  
0
Mode  
Normal  
Test  
A7  
(for precharge PD)  
Slow exit (DLL off)  
Fast exit (DLL on)  
0
1
Read Burst Type  
Nibble sequential  
Interleave  
A3  
0
0
1
Yes  
1
1
MRS Mode  
MR0  
BA1  
0
BA0  
0
BL  
A1  
0
A0  
0
8
MR1  
0
1
4 or 8 (OTF)  
4
0
1
MR2  
1
0
1
0
MR3  
1
1
Reserved  
1
1
WR for autoprecharge  
A11  
0
A10  
A9  
CAS Latency  
A6  
0
A5  
A4  
0
A2  
0
Reserved  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved  
0
0
1
1
0
0
1
1
5
0
Reserved  
0
1
0
6
0
6
7
0
0
0
7
0
0
1
0
8
10  
1
8
1
0
0
1
9
1
1
0
12  
1
10  
11  
1
0
0
Reserved  
1
1
1
0
Note1. BA2 and A13 are reserved for future use and must be programmed to 0 during MRS.  
Note2. WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK (in  
ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in  
the mode register must be programmed to be equal or larger than WRmin. The programmed WR value  
is used with tRP to determine tDAL  
.
Jul. 2012  
33/41  
www.eorex.com  
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