EM47FM3288SBB
Initialization
The following sequence is required for power-up and initialization and is shown in below Figure:
1. Apply power (/RESET is recommended to be maintained below 0.2 x VDD; all other inputs may be
undefined). /RESET needs to be maintained for minimum 200 us with stable power. CKE is pulled “Low”
anytime before /RESET being de-asserted (min. time 10 ns). The power voltage ramp time between 300 mv to
VDDmin must be no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.
• VDD and VDDQ are driven from a single power converter output, AND
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In
addition, VTT is limited to 0.95 V max once power ramp is finished, AND
• Vref tracks VDDQ/2. OR
• Apply VDD without any slope reversal before or at the same time as VDDQ.
• Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After /RESET is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM
will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, /CK) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE
goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also,
a NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once
the CKE is registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization
sequence is finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as /RESET is asserted.
Further, the SDRAM keeps its on-die termination in high impedance state after /RESET de-assertion until CKE
is registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH.
When CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If
RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT
input signal remains static until the power up initialization sequence is finished, including the expiration of
tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register. (tXPR=max (tXS ; 5 x tCK
)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide
“Low” to BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide
“Low” to BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable"
Jul. 2012
31/41
www.eorex.com
EOREX [ EOREX CORPORATION ]
