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EM47FM3288SBB 参数 Datasheet PDF下载

EM47FM3288SBB图片预览
型号: EM47FM3288SBB
PDF下载: 下载PDF文件 查看货源
内容描述: 16GB ( 64mA的?? 8Bankà ?? 32 ),双数据速率3 SDRAM堆叠 [16Gb (64M×8Bank×32) Double DATA RATE 3 Stack SDRAM]
分类和应用: 动态存储器
文件页数/大小: 41 页 / 1147 K
品牌: EOREX [ EOREX CORPORATION ]
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EM47FM3288SBB  
2. CKE Truth Table  
CKE  
Command (n)  
Current State  
Power Down  
Self Refresh  
Action (n)  
Notes  
/RAS, /CAS, /WE, /CS  
X
n-1  
L
n
L
H
L
H
L
L
L
L
L
L
L
Maintain power down  
Power down exit  
14,15  
L
DESELECT or NOP  
X
11,14  
L
Maintain self refresh  
Self refresh exit  
15,16  
L
DESELECT or NOP  
DESELECT or NOP  
DESELECT or NOP  
DESELECT or NOP  
DESELECT or NOP  
DESELECT or NOP  
DESELECT or NOP  
REFRESH  
8,12,16  
Bank Active  
Reading  
H
H
H
H
H
H
H
Active power down entry  
Power down entry  
Power down entry  
Power down entry  
11,13,14  
11,13,14,17  
11,13,14,17  
11,13,14,17  
Writing  
Precharging  
Refreshing  
Precharge power down entry 11  
Precharge power down entry 11,13,14,18  
All Banks Idle  
Self refresh  
9,13,18  
10  
For more details with all signals, see “Command Truth Table”  
Note1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock  
edge.  
Note2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge n.  
Note3. Command (n) is the command registered at clock edge n, and ACTION (n) is a result of Command (n),  
ODT is not included here.  
Note4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this  
document.  
Note5. The state of ODT does not affect the states described in this table. The ODT function is not available  
during Self-Refresh.  
Note6. During any CKE transition (registration of CKE H->L or CKE L->H) the CKE level must be maintained  
until 1nCK prior to tCKEmin being satisfied (at which time CKE may transition again).  
Note7. DESELECT and NOP are defined in the “Command Truth Table”.  
Note8. On self-refresh exit DESELECT or NOP commands must be issued on every clock edge occurring  
during the tXS period. Read or ODT commands may be issued only after tXSDLL is satisfied.  
Note9. Self-Refresh mode can only be entered from the All Banks Idle state.  
Note10. It must be a legal command as defined in the “Command Truth Table”.  
Note11. Valid commands for power-down entry and exit are NOP and DESELECT only.  
Note12. Valid commands for self-refresh exit are NOP and DESELECT only.  
Note13. Self-Refresh can not be entered during Read or Write operations.  
Note14. The Power-Down does not perform any refresh operations.  
Note15. “X” means “don’t care“ (including floating around VREF) in Self-Refresh and Power-Down. It also  
applies to Address pins.  
Note16. VREF (Both VREFDQ and VREFCA) must be maintained during Self-Refresh operation. VREFDQ  
supply may be turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh  
Jul. 2012  
29/41  
www.eorex.com  
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