EM47FM3288SBB
proper ODT operation. For more detailed information on DLL Disable operation refers to “DLL-off Mode”.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be
disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2}
to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at
DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT
externally.
ODT Rtt Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal
termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be programmed in MR2 to
enable a unique RTT value when ODT is enabled during writes. The Rtt_WR value can be applied during writes
even when Rtt_Nom is disabled.
Additive Latency
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR3 SDRAM. In this operation, It allows a read or write command (either with or without
auto-precharge) to be issued immediately after the active command. The command is held for the time of the
Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of
the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS
Write Latency (CWL) register settings.
Write Leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands, addresses, control
signals, and clocks. The fly-by topology has the benefit of reducing the number of stubs and their length, but it
also causes flight time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for
the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the DDR3 SDRAM supports a
‘write leveling’ feature to allow the controller to compensate for skew.
Output Disable
The outputs may be enabled/disabled by MR1 (bit A12). When this feature is enabled (A12 = 1), all output pins
(DQs, DQS, /DQS, etc.) are disconnected from the device, thus removing any loading of the output drivers.
For normal operation, A12 should be set to ‘0’.
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