EM47FM3288SBB
refresh. Upon Self-Refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit
ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after
self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of
tZQoper, tZQinit, or tZQCS between the devices.
ZQ Calibration Timing
ZQ Calibration Method
The ZQ calibration in DDR3 is used both for the output driver and the ODT. The ZQ ball of each DRAM is
connected to an external precision (±1%) 240Ω resistor. This resistor may be shared among devices as long as
the controller does not overlap any timing associated with the calibration and as long as the capacitive loading
does not exceed specification.
Pull-up Calibration
The calibration control block consists of an analog-to-digital converter (ADC), comparators, a majority filter, an
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