EM47FM3288SBB
Recommended DC Operating Conditions
(VDD,VDDQ=1.5V±0.075V)
-125
-150
Symbol
Parameter & Test Conditions
Units
mA
Max
Operating One Bank Active-Read-Precharge Current:
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see
timing used table; BL: 81; AL: 0; /CS: High between ACT, RD and
PRE; Command, Address, Data IO: partially toggling; DM:stable at 0;
Bank Activity: Cycling with one bank active at a time; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD1
TBD
TBD
Precharge Power-Down Current Fast Exit:
CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: stable at 0; Data IO:
FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Pre-charge Power Down Mode: Fast Exit
IDD2P1
TBD
TBD
mA
Precharge Standby Current:
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: partially toggling; Data
IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal:
stable at 0
IDD2N
TBD
TBD
TBD
TBD
mA
mA
Active Power-Down Current:
CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: stable at 0; Data IO:
FLOATING; DM: stable at 0; Bank Activity: all banks open; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD3P
Operating Burst Write Current:
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: High between WR; Command, Address: partially toggling;
Data IO: seamless write data burst with different data between one
burst and the next one; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH
IDD4W
TBD
TBD
mA
Operating Burst Read Current:
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: High between RD; Command, Address: par-tially toggling;
Data IO: seamless read data burst with different data between one
burst and the next one; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD4R
TBD
TBD
TBD
TBD
mA
mA
Burst Refresh Current:
CKE: High; External clock: On; tCK, CL, nRFC: see timing used
table; BL: 8; AL: 0; /CS: High between REF; Command, Address:
partially toggling; Data IO: FLOATING; DM: stable at 0; Bank Activity:
REF command every nRFC; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
IDD5B
Jul. 2012
15/41
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