EM47FM3288SBB
-125
-150
Symbol
Parameter & Test Conditions
Units
Max
Self Refresh Current: Normal Temperature Range; TCASE: 0-
85°C; Auto Self-Refresh (ASR): Disabled; Self-Refresh
Temperature Range (SRT): Normal; CKE: Low; External clock: Off;
IDD6
CK and /CK: LOW; CL: see timing used table; BL: 8; AL: 0; CS, TBD
Command, Address, Data IO: FLOATING; DM: stable at 0; Bank
Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: FLOATING
TBD
mA
Operating Bank Interleave Read Current; CKE: High; External
clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see timing
used table; BL: 8; AL: CL-1; CS: High between ACT and RDA;
Command, Address: partially toggling; Data IO: read data bursts
with different data between one burst and the next one; DM: stable
IDD7
TBD
TBD
mA
at 0; Bank Activity: two times interleaved cycling through banks (0,
1, ...7) with different addressing; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
Note 1: Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
Note 2: Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
Note 3: Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
Note 4: Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
Note 5: Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature
range
Note 6: Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements
are supported by DDR3 SDRAM
Note 7: Read Burst type: Nibble Sequential, set MR0 A[3]=0B
Jul. 2012
16/41
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