欢迎访问ic37.com |
会员登录 免费注册
发布采购

EN29GL064T-70TIP 参数 Datasheet PDF下载

EN29GL064T-70TIP图片预览
型号: EN29GL064T-70TIP
PDF下载: 下载PDF文件 查看货源
内容描述: 64兆位( 8192K ×8位/ 4096K ×16位)闪存 [64 Megabit (8192K x 8-bit / 4096K x 16-bit) Flash Memory]
分类和应用: 闪存
文件页数/大小: 66 页 / 3236 K
品牌: EON [ EON SILICON SOLUTION INC. ]
 浏览型号EN29GL064T-70TIP的Datasheet PDF文件第26页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第27页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第28页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第29页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第31页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第32页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第33页浏览型号EN29GL064T-70TIP的Datasheet PDF文件第34页  
Preliminary EN29GL064  
RY/BY#  
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in  
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the  
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together  
in parallel with a pull-up resistor to VCC. This feature allows the host system to detect when data is ready  
to be read by simply monitoring the RY/BY# pin, which is a dedicated output and controlled by CE# (not  
OE#).  
Hardware Reset  
The RESET# input provides a hardware method of resetting the device to reading array data. When  
RESET# is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately  
terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores  
all read/write commands for the duration of the RESET# pulse. The device also resets the internal state  
machine to reading array data.  
To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the  
device is ready to accept another command sequence.  
When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but  
not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which  
enables the system to read the boot-up firmware from the Flash memory upon a system reset.  
Software Reset  
Software reset is part of the command set that also returns the device to array read mode and must be  
used for the following conditions:  
1. To exit Autoselect mode  
2. When DQ5 goes high during write status operation that indicates program or erase cycle was not  
successfully completed  
3. Exit sector lock/unlock operation.  
4. To return to erase-suspend-read mode if the device was previously in Erase Suspend mode.  
5. After any aborted operations  
The following are additional points to consider when using the reset command:  
This command resets the sectors to the read and address bits are ignored.  
Reset commands are ignored during program and erase operations.  
The reset command may be written between the cycles in a program command sequence before  
programming begins (prior to the third cycle). This resets the sector to which the system was writing  
to the read mode.  
If the program command sequence is written to a sector that is in the Erase Suspend mode, writing  
the reset command returns that sector to the erase-suspend-read mode.  
The reset command may be written during an Autoselect command sequence.  
If a sector has entered the Autoselect mode while in the Erase Suspend mode, writing the reset  
command returns that sector to the erase-suspend-read mode.  
If DQ1 goes high during a Write Buffer Programming operation, the system must write the “Write to  
Buffer Abort Reset” command sequence to RESET the device to reading array data. The standard  
RESET command does not work during this condition.  
This Data Sheet may be revised by subsequent versions  
or modifications due to changes in technical specifications.  
©2004 Eon Silicon Solution, Inc., www.eonssi.com  
30  
Rev. A, Issue Date: 2009/3/20  
 复制成功!