Preliminary EN29GL064
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 14-1. These commands invoke the
Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and verifies the entire memory to an all zero data
pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh.
The system is not required to provide any controls or timings during these operations.
When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7 or
DQ6/DQ2. Refer to “Write Operation Status” for information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware
reset immediately terminates the erase operation. If that occurs, the chip erase command sequence
should be reinitiated once that sector has returned to reading array data, to ensure the entire array is
properly erased.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. The sector address is required when
writing this command. This command is valid only during the sector erase operation. The Sector Erase
Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm.
Addresses are don’t-cares when writing the Sector Erase Suspend command.
When the Erase Suspend command is written during the sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the device enters the erase-suspend-read mode. The
system can read data from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors
produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-read
mode. The system can determine the status of the program operation using write operation status bits,
just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer
to Write Buffer Programming on page 15 and the Autoselect on page 12 for details.
To resume the sector erase operation, the system must write the Erase Resume command. The
address of the erase-suspended sector is required when writing this command. Further writes of the
Resume command are ignored. Another Erase Suspend command can be written after the chip has
resumed erasing.
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation
or a “Write to Buffer” programming operation so that data can read from any non-suspended sector.
When the Program Suspend command is written during a programming process, the device halts the
programming operation within 15 µs maximum (5 µs typical) and updates the status bits. Addresses are
“don't-cares” when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from any
nonsuspended sector. The Program Suspend command may also be issued during a programming
operation while an erase is suspended. In this case, data may be read from any addresses not within a
sector in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area,
then user must use the proper command sequences to enter and exit this region.
The system may also write the Autoselect Command Sequence when the device is in Program Suspend
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
24
Rev. A, Issue Date: 2009/3/20
EON [ EON SILICON SOLUTION INC. ]
