EN29F010
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
JEDEC
Standard
-45
-55
-70
-90
90
Unit
Description
Test Setup
Min
45
55
70
ns
tAVAV
tRC
Read Cycle Time
= V
= V
CE
OE
IL
Max
45
55
70
90
ns
Address to Output Delay
tAVQV
tACC
IL
IL
Max
Max
Max
Max
45
25
10
10
55
30
15
15
70
30
20
20
90
35
20
20
ns
ns
ns
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
= V
OE
Output Enable to Output High Z
Output Hold Time from
Min
0
0
0
0
ns
tAXQX
tOH
Addresses,
or ,
CE OE
whichever occurs first
Notes:
For -45, -55
Vcc = 5.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 5.0V ± 10%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level, Input and Output: 0.8 V and 2.0 V
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
22
Rev. A, Issue Date: 2003/10/20
EON [ EON SILICON SOLUTION INC. ]
