EN25QH32
Table 9. Parameter ID (0) (Advanced Information) 4/9
Address (h)
Address
(Bit)
00
Description
(Byte Mode)
Data
Comment
01
02
(1-1-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
01000b
8 dummy clocks
output
03
04
3Ch
05
000b
3Bh
Not Supported
(1-1-2) Fast Read Number of Mode Bits
(1-1-2) Fast Read Opcode
Opcode for single input opcode & address
and dual output data Fast Read.
06
07
3Dh
3Eh
3Fh
15 : 08
16
17
18
19
20
21
22
23
(1-2-2) Fast Read Number of Wait states
(dummy clocks) needed before valid
output
00100b
4 dummy clocks
Not Supported
000b
BBh
(1-2-2) Fast Read Number of Mode Bits
(1-2-2) Fast Read Opcode
Opcode for single input opcode, dual input
address, and dual output data Fast Read.
31 : 24
Table 9. Parameter ID (0) (Advanced Information) 5/9
Address (h)
Description
Address
(Bit)
Data
Comment
(Byte Mode)
Supports (4-4-4) Fast Read
Device supports Quad input opcode &
address and quad output data Fast Read.
0 = not supported
1 = supported
00
0b
01
02
03
Reserved. These bits default to all 1’s
111b
1b
Reserved
40h
0 = not supported
1 = supported
(EQPI Mode)
Supports (2-2-2) Fast Read
Device supports dual input opcode &
address and dual output data Fast Read.
04
05
06
07
Reserved. These bits default to all 1’s
111b
FFh
Reserved
Reserved
Reserved. These bits default to all 1’s
43h : 41h
31 : 08
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.eonssi.com
48
Rev. E, Issue Date: 2012/01/30
EON [ EON SILICON SOLUTION INC. ]
