EM6603
Table 31.register - CIRQD
Bit
Name
Reset
R/W
-
Description
3
RESERVED
RESERVED
DebCK
-
-
-
2
-
-
1
0
0
R/W
R/W
Debouncer clock select (0=2ms : 1=16ms)
Enable interrupt to CPU (1=enabled)
0
INTEN
Figure 11.Interrupt Request generation
IRQ mask bit which can be written to 0 or 1 (1 to enable an interrupt)
interrupt request flag which is set on the input rising edge.
Timer IRQ flag INTTE and prescaler IRQ flag INTPR arrive independent of their mask bits not to loose any
timing information. But the µprocessor will be interrupted only with mask set to 1.
03/02 REV. G/439
19
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