EM6603
Table 24 shows the selection of inputs to the Timer/Event counter.
Table 24.Timer Clock Selection
TEC2
TEC1
TEC0
Timer/Counter clock source
not active
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2048 Hz from prescaler
512 Hz from prescaler
128 Hz from prescaler
32 Hz from prescaler
8 Hz from prescaler
1 Hz from prescaler
PA3 input terminal (see tables 28 and 29)
8.1 Timer/Counter registers
Table 25.Timer control register - TimCtr
Bit
Name
TimAuto
TEC2
Reset
R/W
R/W
R/W
R/W
R/W
Description
3
0
0
0
0
Timer/Counter AUTO reload
Timer/Counter mode 2
Timer/Counter mode 1
Timer/Counter mode 0
2
1
TEC1
0
TEC0
Table 26.LOW Timer Load/Status register - LTimLS (4 low bits)
Bit
Name
Reset
R/W
R/W
R/W
R/W
R/W
Description
3
TL3/TS3
TL2/TS2
TL1/TS1
TL0/TS0
0
0
0
0
Timer load/status bit 3
Timer load/status bit 2
Timer load/status bit 1
Timer load/status bit 0
2
1
0
Table 27.HIGH Timer Load/Status register - HTimLS (4 high bits)
Bit
Name
Reset
R/W
R/W
R/W
R/W
R/W
Description
3
TL7/TS7
TL6/TS6
TL5/TS5
TL4/TS4
0
0
0
0
Timer load/status bit 7
Timer load/status bit 6
Timer load/status bit 5
Timer load/status bit 4
2
1
0
Table 28.PA3 counter input selection register - PA3cnt
bit
Name
Reset
R/W
Description
3
-
-
-
empty
2
1
-
-
0
0
-
empty
Fout
R/W
R/W
System freq. output on STB/RST pad
PA3 input status
0
PA3cntin
Table 29.PA3 counter input selection
PA3cntin
debPAN
IRQedgeR Counter source
0
X
X
0
1
0
1
PA3 debounced rising edge
1
0
0
1
1
PA3 debounced falling edge
PA3 debounced rising edge
PA3 not debounced falling edge
PA3 not debounced rising edge
1
1
1
X ( Don’t care)
03/02 REV. G/439
17
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