ePVP6800
VFD Controller
7.2.15 RE (Interrupt Flags, Wake-up)
a) PAGE 0 (Interrupt Flags, Wake-up Control Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
/WUPC3 /WUPC2 /WUPC1 /WUPC0
R/W-0 R/W-0 R/W-0 R/W-0
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Bit 0 (/WUPC0) : PORTC0 wake-up control,
0/1 ꢂdisable/enable PC0 pin wake-up function
Bit 1 (/WUPC1) : PORTC1 wake-up control, 0/1 ꢂdisable/enable PC1 pin wake-up function
Bit 2 (/WUPC2) : PORTC2 wake-up control,
0/1 ꢂdisable/enable PC2 pin wake-up function
Bit 3 (/WUPC3) : PORTC3 wake-up control,
0/1 ꢂdisable/enable PC3 pin wake-up function
Bit 4 (-)
Bit 5 (-)
Bit 6 (-)
Bit 7(-)
: Not used
: Not used
: Not used
: Not used
7.2.16 RF (Interrupt Flags)
a) PAGE 0 (Interrupt Status Register)
Bit 7
INT4
Bit 6
INT3
Bit 5
INT2
Bit 4
INT1
Bit 3
IR
Bit 2
CNT2
R/W-0
Bit 1
CNT1
R/W-0
Bit 0
TCIF
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NOTE: "1" means interrupt request, "0" means non-interrupt
Bit 0 (TCIF)
Bit 1 (CNT1)
Bit 2 (CNT2)
Bit 3 (IR)
: TCC timer overflow interrupt flag, Set when TCC timer overflows.
: Counter1 timer overflow interrupt flag. Set when Counter1 timer overflows.
: Counter2 timer overflow interrupt flag. Set when Counter2 timer overflows.
: External INT pin interrupt flag. If PORT90 contains a falling /rising edge
(controlled by CONT register) trigger signal, CPU will set this bit.
Bit 4 (INT1)
Bit 5(INT2)
Bit 6 : (INT3)
Bit 7(INT4)
: External INT1 pin interrupt flag, If PORT91 contains a falling edge trigger
signal, CPU will set this bit.
: External INT2 pin interrupt flag. If PORT92 has a falling edge trigger
signal, CPU will set this bit.
: External INT3 pin interrupt flag. If PORT93 has a falling edge trigger
signal, CPU will set this bit.
: External IR interrupt flag. If PORT94 has a falling edge trigger signal, CPU
will set this bit.
This specification is subject to change without further notice.
11.28.2004 (V123) 17 of 47
ELAN [ ELAN MICROELECTRONICS CORP ]
