ePVP6800
VFD Controller
Trigger edge is as shown below:
Signal Trigger
Time out
TCC
COUNTER1
COUNTER2
COUNTER3
COUNTER4
COUNTER5
Time out
Time out
Time out
Time out
Time out
Falling
Rising edge
IR
INT1
INT2
INT3
Falling edge
Falling edge
Falling edge
7.2.17 R10~R3F (General Purpose Registers)
R10 ~ R1F, R20 ~ R3F (Banks 0 ~ 3) : all are general purpose registers.
7.3Special Purpose Registers
7.3.1 A (Accumulator)
Internal data transfer, or instruction operand holding. It is not an addressable register.
7.3.2 CONT (Control Register)
CONT register is readable (CONTR) and writable (CONTW).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P90EG
INT
TS
RETBK
PAB
PSR2
PSR1
PSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:2
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
18 of 47 11. 28.2004 (V1.23)
This specification is subject to change without further notice.
ELAN [ ELAN MICROELECTRONICS CORP ]
