EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.2 R1 (TCC)
The TCC data buffer is Increased by 16.384kHz or by the instruction clock cycle
(controlled by the CONT register). It is written and read by the program as with any
other register.
7.2.3 R2 (Program Counter)
The R2 structure is depicted in the Figure 7-1 below. The configuration structure
generates 4K × 13 external ROM addresses to the corresponding program instruction
codes.
The "JMP" instruction allows direct loading of the low 10 program counter bits.
The "CALL" instruction loads the low 10 bits of the PC, PC+1, and then pushes the data
onto the stack.
"RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the
top of stack.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the
contents of the ninth and tenth bits are cleared to "0.''
"ADD R2,A" allows a relative address to be added to the current PC, and the contents
of the ninth and tenth bits are cleared to "0.''
"TBL" allows a relative address to be added to the current PC, and the contents of the
ninth and tenth bits don't change. The most significant bit (A10~A11) will be loaded
with the contents of bits PS0~PS1 in the status register (R5 Page 0) upon execution of
a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.
If an interrupt is triggered, the program ROM will jump to Address 0x08 at Page 0. The
CPU will store ACC, the status of R3, and R5 Page automatically; and they will be
restored after instruction RETI.
R5 (Page)
CALL
and
Interrupt
A11 A10
A9 A8
A7~A0
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Stack 6
Stack 7
Stack 8
store
ACC, R3, R5 (Page)
restore
RET
RETL
RETI
0
0
0
1
Page 0 00000~003FF
Page 1 00400~007FF
1
0
Page 2 00800~00BFF
Page 3 00C00~00FFF
1
1
Figure 7-1 Program Counter Organization
8 •
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
