EM78P5840N/41N/42N
8-Bit Microcontrollers
7.1.2 IOC Page Register Configuration
IOC Page Registers
Addr
00
IOC Page 0
IOC Page 1
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
01
Reserve
02
Reserve
03
Reserve
04
Reserve
05
06
Port 6 I/O control
Port 7 I/O control
Reserve
Port 6 switches
Port 7 pull high
Reserve
07
08
09
Port 9 I/O control
Reserve
Reserve
0A
0B
0C
Port 9 switches
ADC control
Reserve
Reserve
Reserve
Clock source (CN1)
Prescaler (CN1)
0D
Reserve
0E
0F
Interrupt mask
Interrupt mask
Reserve
Reserve
The IOC registers are special registers. User can use the “IOW” instruction to write
data and the “IOR” instruction to read data.
7.2 Register Operations
7.2.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer.
Any instruction using R0 as a register actually accesses data pointed by the RAM
Select Register (R4).
Example:
Mov A, @0x20 ; store an address at R4 for indirect addressing
Mov 0x04, A
Mov A, @0xAA ; write data 0xAA to R20 at Bank0 through R0
Mov 0x00, A
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
