EM78P5840N/41N/42N
8-Bit Microcontrollers
7 Function Description
7.1 Register Configuration
7.1.1 R Page Register Configuration
R Page Registers
R Page 1
Addr
R Page 0
R Page 2
R Page 3
Reserve
00
01
02
03
04
05
06
Indirect addressing Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
TCC
Reserve
Reserve
Reserve
Reserve
Reserve
PC
Reserve
Page, Status
RAM bank, RSR
Reserve
Reserve
Program ROM page Reserve
PWM Control
PWM1 Duty
Port 6 I/O data
Reserve
PWM1 Control
Duty of PWM1
07
Port 7 I/O data
ADC MSB output data
Reserve
08
09
Reserve
Reserve
Reserve
Reserve
Reserve
PWM1 Period
PWM2 Duty
Port 9 I/O data
PLL, Main clock,
WDTE
PWM2 Control
PWM2 Duty
0A
0B
Reserve
Reserve
Reserve
Reserve
ADC output data buffer
PWM2 Period
0C
0D
0E
0F
Port C I/O data
Reserve
Counter 1 data
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Interrupt flag
Interrupt flag
Reserve
Reserve
10
:
16 bytes
Common registers
1F
20
:
Bank 0
Bank 1
Bank 2
Bank 3
Common registers Common registers Common registers Common registers
32x8 for each bank 32x8 for each bank 32x8 for each bank 32x8 for each bank
3F
Addresses 00~0F with Page 0~Page 3 are special registers. Addresses 10~1F are
global with general purpose memory. Use the MOV instruction to set the MCU to read
data from or write data to these registers directly. This will ignore the RAM bank select
bits (RB1, RB0 in R4 Page 0). Addresses 20~3F are general purpose RAM, but the
bank number must be indicated before accessing data.
6 •
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
