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EM78P5841NP 参数 Datasheet PDF下载

EM78P5841NP图片预览
型号: EM78P5841NP
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 68 页 / 808 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P5840N/41N/42N  
8-Bit Microcontrollers  
5 Pin Description  
Pin Name  
Power  
AVDD  
AVSS  
Clock  
XIN  
I/O  
Description  
-
-
Power supply  
Ground  
I
O
I
Input pin for the 32.768 kHz oscillator  
XOUT  
PLLC  
Output pin for the 32.768 kHz oscillator  
Phase lock loop capacitor. Connect a capacitor (0.047µF to 0.1µF) to ground  
ERIC mode clock signal input. This pin is shared with PLLC.  
OSC  
I
Counter 1 external CLK input. This pin is shared with P94.  
Note that the frequency of the input CLK must be less than 1MHz.  
CIN  
I
10-Bit 8 Channel A/D  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
AD8  
PWM  
PWM1  
PWM2  
IO  
I
I
I
I
I
I
I
I
ADC Input Channel 1. This pin is shared with Port 90.  
ADC Input Channel 2. This pin is shared with Port 91.  
ADC Input Channel 3. This pin is shared with Port 62.  
ADC Input Channel 4. This pin is shared with Port 63.  
ADC Input Channel 5. This pin is shared with Port 64.  
ADC Input Channel 6. This pin is shared with Port 65.  
ADC Input Channel 7. This pin is shared with Port 92.  
ADC Input Channel 8. This pin is shared with Port 93.  
O
O
Pulse width modulation output. This pin is shared with Port C1.  
Pulse width modulation output. This pin is shared with Port C2.  
Each bit in Port 60 and Port 61 can be an input or output port. These two pins  
can be used for the ERIC and IRC modes.  
P60 ~ P61  
P62 ~P65  
I/O  
I/O  
Each bit in Port 62 to Port 65 can be an input or output port.  
P70  
I/O  
I
Each bit in Port 70 can be an input or output port.  
Port 71 is input only  
P71  
P73 ~ P76  
P90 ~ P97  
PC1 ~ PC2  
I/O  
I/O  
I/O  
Each bit in Port 7 can be an input or output port.  
Each bit in Port 9 can be an input or output port.  
Each bit in Port C can be an input or output port.  
Interrupt sources. A falling or rising edge signal (controlled by the CONT  
register) in Port 70 will generate an interrupt.  
INT0  
INT1  
(Port 70)  
(Port 71)  
Interrupt sources with the same interrupt flag. A falling edge signal on any pin in  
Port 71 will generate an interrupt.  
Interrupt sources with the same interrupt flag. A falling edge signal on any pin in  
Port 73 will generate an interrupt.  
INT3  
Port 73  
I
/RESET  
Low reset  
4 •  
Product Specification (V1.0) 04.25.2006  
(This specification is subject to change without further notice)