EM78P510N
8-Bit Microcontrollers
Program the same clock rate and clock edge to latch on both the master and slave
devices
The byte received will update the transmitted byte
The RBF (located in Register 0x0C) will be set as the SPI operation is completed
Timing is shown in Fig.6-23 and 6-24
PA5/SEG5/SO:
Serial Data Out
Transmit sequentially; the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last
Program the same clock rate and clock edge to latch on both the master and slave
devices
The received byte will update the transmitted byte
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is
completed
Timing is shown in Fig.6-23 and 6-24
PA6/SEG6/SCK:
Serial Clock
Generated by a master device
Synchronize the data communication on both the SI and SO pins
The CES (located in Register 0x0D) is used to select the edge to communicate.
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication
The CES, SBR0, SBR1, and SBR2 bits have no effect in slave mode
Timing is show in Fig.6-23 and 6-24
PA7/SEG7//SS:
Slave Select; negative logic
Generated by a master device to signify the slave(s) to receive data
Goes low before the first cycle of SCK appears, and remains low until the last
(eighth) cycle is completed
Ignores the data on the SI and SO pins while /SS is high, because the SO is no
longer driven
Timing is shown in Fig.6-23 and 6-24
80 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
