EM78P510N
8-Bit Microcontrollers
Below are the functions of each block and explanations on how to carry out the SPI
communication with the signals depicted in Fig.6-22 and Fig.6-23.
PA4/SEG4/SI:Serial Data In
PA5/SEG5/SO:Serial Data Out
PA6/SEG6/SCK:Serial Clock
PA7/SEG7//SS:/Slave Select (Option). This pin (/SS) may be required during a
slave mode
RBF: Set by Buffer Full Detector, and reset by software
Buffer Full Detector: Set to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift
SPIS reg.:Shifting byte in and out. The MSB is shifted first. Both the SPIS and the
SPIW registers are loaded at the same time. Once data are written, SPIS starts
transmission / reception. The data received will be moved to the SPIR register as
the shifting of the 8-bit data is completed. The RBF (Read Buffer Full) flag and the
RBFI (Read Buffer Full Interrupt) flag are then set.
SPIR reg.:Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
SPIW reg.:Write buffer. The buffer will deny any attempts to write until the 8-bit
shifting is completed.
The SSE bit will be kept in “1“ if the communication is still undergoing. This flag must
be cleared as the shifting is completed. Users can determine if the next write attempt is
available.
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
Clock Select:Selecting either the internal or the external clock as the shifting clock.
Edge Select:Selecting the appropriate clock edges by programming the CES bit
6.12.3 SPI Signal & Pin Description
The detailed functions of the four pins, SI, SO, SCK, and /SS are as follows:
PA4/SEG4/SI:
Serial Data In,
Receive sequentially, the Most Significant Bit (MSB) first, Least Significant Bit
(LSB) last,
Defined as high-impedance, if not selected
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
