EM78P510N
8-Bit Microcontrollers
6.2.28 Bank 2 R6 TSR (Timer Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1MOD
TRCB
T1CSS1 T1CSS0
T2CSS
T1EN
T1OMS
T1OC
Bit 7 (T1MOD): Timer Operates Mode Select Bit
0 : Two 8-bit Timer
1 : Timer 1 and Timer 2 cascade to one 16-bit Timer
NOTE
By setting T1MOD to “1”, Timer can cascade to one 16-bit Timer. This 16 bits Timer
is controlled by Time r1, including enable, clock source and prescaler. Timer 1 is
MSB and Timer 2 is LSB in value of period and duty.
Bit 6 (TRCB): Timers 1, 2 Read Control Bit
0: When this bit set to 0, read data from T1PD or T2PD.
1: When this bit set to 1, read data from T1PD or T2PD, but this is
value of timer counter.
Bits 5~4 (T1CSS1~T1CSS0): Timer 1 Clock Source Select Bits
T1CSS1 T1CSS0 Timer 1 Clock Source Select
0
0
1
0
1
X
Fm
Fs
T1CK
Bit 3 (T2CSS): Timer 2 Clock Source Select Bit
0 : Main clock with prescaler
1 : Sub clock with prescaler
Bit 2 (T1EN): Timer 1 Start Bit
0 : Timer 1 stop
1 : Timer 1 start
Bit 1 (T1OMS): Timer 1 Output Mode Select Bit
0 : Repeating mode
1 : One–shot mode
NOTE
One-shot mode is only used in Timer 1, Capture and PWM1 modes.
24 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)