EM78P510N
8-Bit Microcontrollers
Bit 4 (SSE): SPI Shift Enable Bit
0 : Reset as soon as the shift is complete, and the next byte is read to
shift.
1 : Start to shift, and remain on “1” while the current byte is still being
transmitted.
Bit 3 (SDOC): SDO Output Status Control Bit
0 : After the serial data output, the SDO remain high.
1 : After the serial data output, the SDO remain low.
Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate Select Bits
SBRS2
SBRS1
SBRS0
Mode
Master
Master
Master
Master
Master
Master
Slave
SPI Baud Rate
Fosc/2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Timer2
/SS enable
/SS disable
Slave
6.2.36 Bank 2 RE SPIR (SPI Read Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
Bits 7~0 (SRB7~SRB0): SPI Read Data Buffer
6.2.37 Bank 2 RF SPIW (SPI Write Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Bits 7~0 (SWB7~SWB0): SPI Write Data Buffer
28 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
