EM78P510N
8-Bit Microcontrollers
6.2.24 Bank 1 RC LCDSCR2 (LCD Segment Control Register 2)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
Bit 7: Reserved
Bits 6~0 (SEG22~SEG16): LCD Segment 22~16 Control Bits
0 : Disable, functions as normal I/O or other functions
1 : Enable, functions as LCD common driver pins
6.2.25 Bank 1 RE EIMR (External Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIE7
EXIE6
EXIE5
EXIE4
EXIE3
EXIE2
EXIE1
EXIE0
Bits 7~0 (EXIE7~EXIE0): Interrupt Enable Bit. Enable interrupt source respectively.
External interrupt
Digital Noise
INT Pin Secondary Function Pin Enable Condition
Edge
Reject
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
2/Fc
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
PB3, SEG11
ENI+EXIE7(EIMR7)
ENI+EXIE6(EIMR6)
ENI+EXIE5(EIMR5)
ENI+EXIE4(EIMR4)
ENI+EXIE3(EIMR3)
ENI+EXIE2(EIMR2)
ENI+EXIE1(EIMR1)
ENI+EXIE0(EIMR0)
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
Rising or Falling
PB2, SEG10, AD11
PB1, SEG9, AD10
PB0, SEG8, AD9
P77, T1CAP
P76, T1CK
P75, T1OUT, PWM1
P74, SEG18
INT7~INT0: Pulse less than 2/Fc is eliminated as noise. Pulse less than 5/Fc is
eliminated as noise.
6.2.26 Bank 1 RF EISR (External Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EXIF7
EXIF6
EXIF5
EXIF4
EXIF3
EXIF2
EXIF1
EXIF0
These bits are set to “1” when interrupt occurs respectively.
Bits 7~0 (EXIF7~EXIF0): Interrupt Flag when External Interrupt 7~0 occur
22 •
Product Specification (V0.9) 09.12.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
