EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of ADC oscillator clock rate
00 = 1: 16 (default value)
01 = 1: 4
10 = 1: 64
11 = 1: WDT ring oscillator frequency
CKR1:CKR0
Operation Mode
Fosc/16
Max. Operation Frequency
00
01
10
11
4 MHz
1 MHz
16MHz
-
Fosc/4
Fosc/64
Internal RC
Bit 4 (ADRUN): ADC starts to RUN.
0 = Reset upon completion of the conversion. This bit cannot be
reset through software
1 = an AD conversion is started. This bit can be set by software
Bit 3 (ADPD): ADC Power-down mode
0 = Switch off the resistor reference to save power even while the
CPU is operating
1 = ADC is operating
Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select
000 = AIN0/P60
001 = AIN1/P61
010 = AIN2/P62
011 = AIN3/P63
100 = AIN4/P64
101 = AIN5/P65
110 = AIN6/P66
111 = AIN7/P67
These bits can only be changed when the ADIF bit (see Section
6.1.14) and the ADRUN bit are both LOW.
6.1.30 Bank 2 RA (ADOC: ADC Offset Calibration Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CALI
SIGN
VOF[2]
VOF[1]
VOF[0]
“0”
“0”
“0”
Bit 7 (CALI):
Calibration enable bit for ADC offset
0 = Disable Calibration
1 = Enable Calibration
22 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
