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EM78P351NK 参数 Datasheet PDF下载

EM78P351NK图片预览
型号: EM78P351NK
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: OTP只读存储器
文件页数/大小: 110 页 / 1823 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P350N  
8-Bit Microprocessor with OTP ROM  
6.1.34 Bank 2 RE (LVDC: LVD Control Register )  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
“0”  
“0”  
“0”  
“0”  
LVDEN  
/LVD  
LVD1  
LVD0  
There is no LVD function in the ICE350N simulator.  
Bits 7 ~ 4: Not used, set to “0” at all time.  
Bit 3 (LVDEN): Low Voltage Detect Register  
0 : disable LVD  
1 : enable LVD  
Bit 2 (/LVD): Low Voltage Detector. This is a read only bit. When the Vdd pin voltage is  
lower than the LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be  
cleared.  
0 : If Vdd < .LVD voltage interrupt level  
1 : If Vdd > LVD voltage interrupt level  
Bits 1 ~ 0 (LVD1 ~ LVD0) : Low Voltage Detect level select bits  
LVDEN  
<RE,3>  
LVD1, LVD0  
<RE,1,0>  
LVD Voltage Interrupt Level  
LVDIF  
1
1
1
1
0
11  
10  
01  
00  
XX  
2.2V  
3.3V  
4.0V  
4.5V  
NA  
1*  
1*  
1*  
1*  
0
*If Vdd has crossover at LVD voltage interrupt level as Vdd changes, LVDIF =1.  
6.1.35 Bank 2 RF (TMR3H: Most Significant Bits (Bit 9 ~ Bit 2) of  
PWM3 Timer)  
The contents of RF are read-only.  
6.1.36 Bank3 R5 (Pull-low Control Register 1)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
/PL57  
/PL56  
/PL55  
/PL54  
/PL53  
/PL52  
/PL51  
/PL50  
Bank 3 R5 register is both readable and writable.  
Bit 7 (/PL57): Control bit is used to enable the pull-high of the P57 pin.  
0 = Enable pull-low output  
1 = Disable pull-low output  
Bit 6 (/PL56): Control bit is used to enable the pull-low function of the P56 output pin.  
Bit 5 (/PL55): Control bit is used to enable the pull-low function of the P55 output pin.  
Bit 4 (/PL54): Control bit is used to enable the pull-low function of the P54 output pin.  
Bit 3 (/PL53): Control bit is used to enable the pull-low function of the P53 output pin.  
Bit 2 (/PL52): Control bit is used to enable the pull-low function of the P52 output pin.  
Bit 1 (/PL51): Control bit is used to enable the pull-low function of the P51 output pin.  
Bit 0 (/PL50): Control bit is used to enable the pull-low function of the P50 output pin.  
24 •  
Product Specification (V1.0) 09.14.2006  
(This specification is subject to change without further notice)  
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