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EM78P350N 参数 Datasheet PDF下载

EM78P350N图片预览
型号: EM78P350N
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: OTP只读存储器
文件页数/大小: 110 页 / 1823 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P350N  
8-Bit Microprocessor with OTP ROM  
6.17 Instruction Set  
Each instruction in the instruction set is a 13-bit word divided into an OP code and one  
or more operands. Normally, all instructions are executed within one single instruction  
cycle (one instruction consists of 2 oscillator time periods), unless the program counter  
is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or  
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,  
these instructions need one or two instruction cycles as determined by Code Option  
Register CYES bit.  
In addition, the instruction set has the following features:  
1. Every bit of any register can be set, cleared, or tested directly.  
2. The I/O registers can be regarded as general registers. That is, the same  
instruction can operate on I/O registers.  
Convention:  
R = Register designator that specifies which one of the registers (including operation and general purpose  
registers) is to be utilized by the instruction.  
b = Bit field designator that selects the value for the bit located in the register R and which affects the  
operation.  
k = 8 or 10-bit constant or literal value  
Status  
Binary Instruction  
HEX  
Mnemonic  
Operation  
No Operation  
Affected  
None  
C
0 0000 0000 0000  
0 0000 0000 0001  
0 0000 0000 0010  
0 0000 0000 0011  
0 0000 0000 0100  
0 0000 0000 rrrr  
0 0000 0001 0000  
0 0000 0001 0001  
0 0000 0001 0010  
0 0000 0001 0011  
0 0000 0001 0100  
0 0000 0001 rrrr  
0 0000 01rr rrrr  
0 0000 1000 0000  
0 0000 11rr rrrr  
0 0001 00rr rrrr  
0 0001 01rr rrrr  
0 0001 10rr rrrr  
0 0001 11rr rrrr  
0000  
0001  
0002  
0003  
0004  
000r  
0010  
0011  
0012  
0013  
0014  
001r  
00rr  
NOP  
DAA  
Decimal Adjust A  
A CONT  
CONTW  
SLEP  
WDTC  
IOW R  
ENI  
None  
T, P  
0 WDT, Stop oscillator  
0 WDT  
T, P  
A IOCR  
None1  
None  
None  
None  
Enable Interrupt  
Disable Interrupt  
[Top of Stack] PC  
DISI  
RET  
RETI  
[Top of Stack] PC, Enable Interrupt None  
CONTR  
IOR R  
CONT A  
IOCR A  
None  
None1  
None  
Z
MOV R,A A R  
0080  
00rr  
CLRA  
0 A  
0 R  
CLR R  
Z
01rr  
SUB A,R R-A A  
SUB R,A R-A R  
Z,C, DC  
Z,C, DC  
Z
01rr  
01rr  
DECA R  
DEC R  
R-1 A  
R-1 R  
01rr  
Z
88 •  
Product Specification (V1.0) 09.14.2006  
(This specification is subject to change without further notice)  
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