EM78P350N
8-Bit Microprocessor with OTP ROM
6.15 LVD (Low Voltage Detector)
During the power source unstable situation, such like external power noise interference
of EMS test condition, it will cause the power vibrate fierce. At the time the Vdd is
unsettled, it may be below working voltage. When system supplies voltage, Vdd, below
the working voltage, the IC kernel must keep all register status automatically. LVD
property is setting at Register RE, Bit 1, 0 detail operation mode as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
“0”
LVDEN
/LVD
LVD1
LVD0
Bits 1 ~ 0 (LVD1 ~ LVD0): Low Voltage Detect level control Bits.
LVDEN
<RA, 2>
LVD1,LVD0
<RA, 1, 0>
LVD Voltage Interrupt Level
LVDIF
1
1
1
1
0
11
10
01
00
XX
2.2V
3.3V
4.0V
4.5V
NA
1*
1*
1*
1*
0
* If Vdd has crossover at LVD voltage interrupt level as Vdd changes, LVDIF =1.
The LVD status and interrupt flag is referred to as RF
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RF
“0”
“0”
“0”
LVDIF ADWE CMPWE ICWE PWMWE
Note: “1” means with interrupt request
“0” means no interrupt occurs
Bit 4 (LVDIF): Low Voltage Detector Interrupt Register
The following steps are needed to setup the LVD function:
Set the LVDEN of Register RE of Bank 2 to”1”, then use Bit 1, 0 (LVD1, LVD0) of
Register RE of Bank 2 to set the LVD interrupt level while waiting for an interrupt to
occur.
The internal LVD module is using internal circuit to fit. When you set the LVDEN enable
the LVD module. The current consumption will increase about 10µA. During sleep
mode, the LVD module continues to operate. If the device voltage drops slowly and
crosses the detect point, the LVDIF bit will be set and device won’t wake up from sleep
time. Until the other wake-up source of EM78P350N, the LVD interrupt flag still set as
the prior status.
When the system resets, the LVD flag will be cleared.
When Vdd drops not below VLVD, LVDIF remains at “0”.
84 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)