EM78P350N
8-Bit Microprocessor with OTP ROM
When Vdd drops below VLVD, LVDIF is set to “1”. If in global ENI enable, LVDIF will be
set to “1”, the next instruction will branch to an interrupt vector. The LVD interrupt flag is
cleared to “0” by software.
When Vdd drops below VRESET to less than 80µs, the system will ignore it and keep
going. When Vdd drops below VRESET to more than 80µs, a system reset will occur.
Refer to Section 6.5.1 for Reset description.
6.16 Code Option
The EM78P350N has two Code option words and one Customer ID word that are not
part of the normal program memory.
Word 0
Word 1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
6.16.1 Code Option Register (Word 0)
Word 0
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
-
LVR1 LVR0 LCE CLKS ENWDTB OSC2 OSC1 OSC0 HLP PR2 PR1 PR0
Bit 12: Unimplemented, read as “0”.
Bits 11 ~ 10: Low voltage reset enable bits.
LVR1, LVR0
Reset Level
Release Level
00
01
10
11
4.0V
3.5V
2.7V
NA
4.2V
3.7V
2.9V
NA
If VDD < 1.8V, the IC will be reset.
If VDD < 2.7V, the IC will be reset.
If VDD < 3.5V, the IC will be reset.
If VDD < 4.0V, the IC will be reset.
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
